1. Field of the Invention
The present invention relates to an electrostatic discharge protective circuit. More particularly, the present invention relates to an electrostatic discharge protective circuit under a conductive pad.
2. Description of the Related Art
Electrostatic discharge (ESD) is one of the major ways for an integrated circuit (IC) to be damaged in an IC fabrication process. This is especially true for fabrication of a deep sub-micron IC. In order to overcome the problems caused by static electricity, an ESD protective circuit is incorporated on the input/output (I/O) pads of a complementary metal-oxide-semiconductor (CMOS) IC through an on-chip method. However, the protection provided by the ESD protective circuit becomes less effective as the line width of the semiconductor fabrication process is downsized.
FIG. 1A is a schematic circuit diagram of a conventional ESD protective circuit. As shown in FIG. 1A, in order to protect the internal circuit 10, the ESD current imported through an input port INP is discharged through an NMOS transistor N1 to a ground V.sub.SS. FIG. 1B is a schematic circuit diagram of another conventional ESD protective circuit. As shown in FIG. 1B, in order to protect the internal circuit 10, the ESD current can be discharged not only through an NMOS transistor N1 to the ground V.sub.SS but also through a PMOS transistor P1 to a voltage source V.sub.DD.
FIG. 2 is a schematic, cross-sectional view of the ESD protective circuit in FIG. 1A. As shown in FIG. 2, the NMOS transistor N1 comprises a substrate 20, a drain region 22 coupled to an input line I/P through a contact plug 24, a source region 26 coupled to the ground V.sub.SS through a contact plug 28 and a gate 29 between the source region 26 and the drain region 22. The gate 29 is also coupled to the ground V.sub.SS through a contact plug 28.
FIG. 3 is a schematic, top view of the ESD protective circuit in FIG. 2. The cross-sectional view taken along the line I-I' in FIG. 3 is denoted as FIG. 2. As shown in FIG. 3, there is an input (I/P) pad 30 beside the input line I/P. The I/P pad 30 is coupled to the input line I/P, the input port INP (as shown in FIG. 1A) and the internal circuit (as shown in FIG. 1A).
The conventional ESD protective circuit is formed beside the I/P pad 30 in a limited area. It is necessary to keep the predetermined spaces of the design rule between source region and node contact hole and between the source region and the gate, so that the area of the ESD protective circuit is large. Therefore, the size of the chip is large. For the design of Ultra Large Scale Integration (ULSI) circuit, it is important to reduce the size of the chip as the size of the device is gradually decreased.